/**
 ******************************************************************************
 * @file    pmu.h
 * @author  hyseim software Team
 * @date    18-Aug-2023
 * @brief   This file provides all the headers of the pmu functions.
 ******************************************************************************
 * @attention
 *
 * Copyright (c) 2020 Hyseim. Co., Ltd.
 * All rights reserved.
 *
 * This software is licensed under terms that can be found in the LICENSE file
 * in the root directory of this software component.
 * If no LICENSE file comes with this software, it is provided AS-IS.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __PMU_H__
#define __PMU_H__

#define PD_CA7_0_PWR_BIT  ( 1 << 0 )
#define PD_CA7_1_PWR_BIT  ( 1 << 1 )
#define PD_CA7_2_PWR_BIT  ( 1 << 2 )
#define PD_CA7_3_PWR_BIT  ( 1 << 3 )
#define PD_SCU_PWR_BIT    ( 1 << 4 )
#define PD_CPUL_PWR_BIT   ( 1 << 5 )
#define PD_DDR_PWR_BIT    ( 1 << 6 )
#define PD_NPU_PWR_BIT    ( 1 << 7 )
#define PD_VPU_PWR_BIT    ( 1 << 8 )
#define PD_LCDC_PWR_BIT   ( 1 << 9 )
#define PD_ISP_PWR_BIT    ( 1 << 10)
#define PD_OTG_PWR_BIT    ( 1 << 11)
#define PD_DSP_PWR_BIT    ( 1 << 12)
#define PD_CRYPTO_PWR_BIT ( 1 << 13)
#define CHIP_PWR_BIT      ( 1 << 14)

void pmu_allpd_repower (void);
void pmu_cpul_repower (void);
void pmu_pd_up(int pd_bit);
void pmu_pd_down(int pd_bit);
void pmu_pd_repower(int pd_bit);
//-------------------------------------------------------------------------------
//define address offset
//-------------------------------------------------------------------------------

#define                 PMU_WAKEUP_CFG0_LO           0x00
#define                 PMU_WAKEUP_CFG0_HI           0x04
#define                 PMU_WAKEUP_CFG1_LO           0x08
#define                 PMU_WAKEUP_CFG1_HI           0x0c
#define                 PMU_WAKEUP_CFG2_LO           0x10
#define                 PMU_WAKEUP_CFG2_HI           0x14
#define                 PMU_PWRDN_CON_LO             0x18
#define                 PMU_PWRDN_CON_HI             0x1c
#define                 PMU_PWRDN_ST                 0x20
#define                 PMU_PWRMODE_CORE_CON_LO      0x24
#define                 PMU_PWRMODE_CORE_CON_HI      0x28
#define                 PMU_PWRMODE_COMMON_CON_LO    0x2c
#define                 PMU_PWRMODE_COMMON_CON_HI    0x30
#define                 PMU_SFT_CON_LO               0x34
#define                 PMU_SFT_CON_HI               0x38
#define                 PMU_INT_CON_LO               0x3c
#define                 PMU_INT_CON_HI               0x40
#define                 PMU_INT_ST                   0x44
#define                 PMU_GPIO_POS_INT_CON_LO      0x48
#define                 PMU_GPIO_POS_INT_CON_HI      0x4c
#define                 PMU_GPIO_NEG_INT_CON_LO      0x50
#define                 PMU_GPIO_NEG_INT_CON_HI      0x54
#define                 PMU_GPIO_POS_INT_ST          0x58
#define                 PMU_GPIO_NEG_INT_ST          0x5c
#define                 PMU_CORE_PWR_ST              0x60
#define                 PMU_BUS_IDLE_REQ_LO          0x64
#define                 PMU_BUS_IDLE_REQ_HI          0x68
#define                 PMU_BUS_IDLE_ST              0x6c
#define                 PMU_BUS_IDLE_ST1             0x70
#define                 PMU_POWER_ST                 0x74
#define                 PMU_OSC_CNT_LO               0x78
#define                 PMU_OSC_CNT_HI               0x7c
#define                 PMU_PLLLOCK_CNT_LO           0x80
#define                 PMU_PLLLOCK_CNT_HI           0x84
#define                 PMU_PLLRST_CNT_LO            0x88
#define                 PMU_PLLRST_CNT_HI            0x8c
#define                 PMU_STABLE_CNT_LO            0x90
#define                 PMU_STABLE_CNT_HI            0x94
#define                 PMU_DDRIO_PWRON_CNT_LO       0x98
#define                 PMU_DDRIO_PWRON_CNT_HI       0x9c
#define                 PMU_WAKEUP_RST_CLR_CNT_LO    0xa0
#define                 PMU_WAKEUP_RST_CLR_CNT_HI    0xa4
#define                 PMU_DDR_SREF_ST              0xa8
#define                 PMU_SYS_REG0_LO              0xac
#define                 PMU_SYS_REG0_HI              0xb0
#define                 PMU_SYS_REG1_LO              0xb4
#define                 PMU_SYS_REG1_HI              0xb8
#define                 PMU_SYS_REG2_LO              0xbc
#define                 PMU_SYS_REG2_HI              0xc0
#define                 PMU_SYS_REG3_LO              0xc4
#define                 PMU_SYS_REG3_HI              0xc8
#define                 PMU_SCU_PWRDN_CNT_LO         0xcc
#define                 PMU_SCU_PWRDN_CNT_HI         0xd0
#define                 PMU_SCU_PWRUP_CNT_LO         0xd4
#define                 PMU_SCU_PWRUP_CNT_HI         0xd8
#define                 PMU_TIMEOUT_CNT_LO           0xdc
#define                 PMU_TIMEOUT_CNT_HI           0xe0
#define                 PMU_CPUBAPM_CON_LO           0xe4
#define                 PMU_INFO_TX_CON_LO           0xe8

static int idle_cfg[15] =
{
 10,//cpub
 10,//cpub
 10,//cpub
 10,//cpub
 10,//cpub
 11,//cpul
 3, //ddr
 4, //7 npu
 5, //8 vpu
 9, //9 lcdc
 8, //10 isp
 7, //11 otg
 6, //12 dsp
 2, //13 crypto
 0  //14 chip
};

#define  IDLE_REQ_CPUL_CFG        ( 0x10000 <<   11 )  |  ( 1 <<   11 )
#define  IDLE_REQ_CPUB_CFG        ( 0x10000 <<   10 )  |  ( 1 <<   10 )
#define  IDLE_REQ_LCDC_CFG        ( 0x10000 <<   9  )  |  ( 1 <<   9  )
#define  IDLE_REQ_ISP_CFG         ( 0x10000 <<   8  )  |  ( 1 <<   8  )
#define  IDLE_REQ_OTG_CFG         ( 0x10000 <<   7  )  |  ( 1 <<   7  )
#define  IDLE_REQ_DSP_CFG         ( 0x10000 <<   6  )  |  ( 1 <<   6  )
#define  IDLE_REQ_VPU_CFG         ( 0x10000 <<   5  )  |  ( 1 <<   5  )
#define  IDLE_REQ_NPU_CFG         ( 0x10000 <<   4  )  |  ( 1 <<   4  )
#define  IDLE_REQ_DDR_CFG         ( 0x10000 <<   3  )  |  ( 1 <<   3  )
#define  IDLE_REQ_CRYPTO_CFG      ( 0x10000 <<   2  )  |  ( 1 <<   2  )
#define  IDLE_REQ_PMU_CFG         ( 0x10000 <<   1  )  |  ( 1 <<   1  )
#define  IDLE_REQ_PERI_CFG        ( 0x10000 <<   0  )  |  ( 1 <<   0  )

#define  IDLE_REL_CPUL_CFG        ( 0x10000 <<   11 )
#define  IDLE_REL_CPUB_CFG        ( 0x10000 <<   10 )
#define  IDLE_REL_LCDC_CFG        ( 0x10000 <<   9  )
#define  IDLE_REL_ISP_CFG         ( 0x10000 <<   8  )
#define  IDLE_REL_OTG_CFG         ( 0x10000 <<   7  )
#define  IDLE_REL_DSP_CFG         ( 0x10000 <<   6  )
#define  IDLE_REL_VPU_CFG         ( 0x10000 <<   5  )
#define  IDLE_REL_NPU_CFG         ( 0x10000 <<   4  )
#define  IDLE_REL_DDR_CFG         ( 0x10000 <<   3  )
#define  IDLE_REL_CRYPTO_CFG      ( 0x10000 <<   2  )
#define  IDLE_REL_PMU_CFG         ( 0x10000 <<   1  )
#define  IDLE_REL_PERI_CFG        ( 0x10000 <<   0  )

#define   IDLE_CPUL      ( 0x10000 <<   11 )
#define   IDLE_CPUB      ( 0x10000 <<   10 )
#define   IDLE_LCDC      ( 0x10000 <<   9  )
#define   IDLE_ISP       ( 0x10000 <<   8  )
#define   IDLE_OTG       ( 0x10000 <<   7  )
#define   IDLE_DSP       ( 0x10000 <<   6  )
#define   IDLE_VPU       ( 0x10000 <<   5  )
#define   IDLE_NPU       ( 0x10000 <<   4  )
#define   IDLE_DDR       ( 0x10000 <<   3  )
#define   IDLE_CRYPTO    ( 0x10000 <<   2  )
#define   IDLE_PMU       ( 0x10000 <<   1  )
#define   IDLE_PERI      ( 0x10000 <<   0  )

#define  IDLE_ACK_CPUL    ( 1 <<   11 )
#define  IDLE_ACK_CPUB    ( 1 <<   10 )
#define  IDLE_ACK_LCDC    ( 1 <<   9  )
#define  IDLE_ACK_ISP     ( 1 <<   8  )
#define  IDLE_ACK_OTG     ( 1 <<   7  )
#define  IDLE_ACK_DSP     ( 1 <<   6  )
#define  IDLE_ACK_VPU     ( 1 <<   5  )
#define  IDLE_ACK_NPU     ( 1 <<   4  )
#define  IDLE_ACK_DDR     ( 1 <<   3  )
#define  IDLE_ACK_CRYPTO  ( 1 <<   2  )
#define  IDLE_ACK_PMU     ( 1 <<   1  )
#define  IDLE_ACK_PERI    ( 1 <<   0  )

#define PD_CA7_0_PWRDWN_BIT  ( 1 << 0 )
#define PD_CA7_1_PWRDWN_BIT  ( 1 << 1 )
#define PD_CA7_2_PWRDWN_BIT  ( 1 << 2 )
#define PD_CA7_3_PWRDWN_BIT  ( 1 << 3 )
#define PD_SCU_PWRDWN_BIT    ( 1 << 4 )
#define PD_CPUL_PWRDWN_BIT   ( 1 << 5 )
#define PD_DDR_PWRDWN_BIT    ( 1 << 6 )
#define PD_NPU_PWRDWN_BIT    ( 1 << 7 )
#define PD_VPU_PWRDWN_BIT    ( 1 << 8 )
#define PD_LCDC_PWRDWN_BIT   ( 1 << 9 )
#define PD_ISP_PWRDWN_BIT    ( 1 << 10)
#define PD_OTG_PWRDWN_BIT    ( 1 << 11)
#define PD_DSP_PWRDWN_BIT    ( 1 << 12)
#define PD_CRYPTO_PWRDWN_BIT ( 1 << 13)
#define CHIP_PWRDWN_BIT      ( 1 << 14)

#define  CPUL_SLEEPDEEP       ( 1 << 10 )
#define  STANDBYWFI_CPU3      ( 1 <<  9 )
#define  STANDBYWFI_CPU2      ( 1 <<  8 )
#define  STANDBYWFI_CPU1      ( 1 <<  7 )
#define  STANDBYWFI_CPU0      ( 1 <<  6 )
#define  STANDBYWFE_CPU3      ( 1 <<  5 )
#define  STANDBYWFE_CPU2      ( 1 <<  4 )
#define  STANDBYWFE_CPU1      ( 1 <<  3 )
#define  STANDBYWFE_CPU0      ( 1 <<  2 )
#define  STANDBYWFIL2_CLUSTER ( 1 <<  1 )
#define  L2FLUSHDONE_CLUSTER  ( 1 <<  0 )
//sanity
#define    CH1_SAR_0            0x100
#define    UART_IER             0x04
#define    T0SVL                0x008
#define    T1SVL                0x028
#define    T2SVL                0x048
#define    T3SVL                0x068
#define    T4SVL                0x088
#define    T5SVL                0x0a8
#define    T0SVH                0x00c
#define    WDT_CR               0x00
#define    ENABLE               VPU_BASE+0x0004
#define    BUSCTRL              VPU_BASE+0x0044
#define    SPACC_IRQ_EN         0x00
#define    PKA_CTRL             0x00
#define    GICD_BASE            GIC_BASE+0x1000
#define    GICD_CTLR            0x0000
#define    IC_SS_SCL_LCNT       0x18
#define    PWM_SRCPOL           0x134
#define    ISP_MIPI_IMSC        ISP_BASE+0x1C00+0x0008
#define    SDMMC_CTRL           0x0000
#define    SCIATRDTIME          SCI_BASE + 0x34

#endif







